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w29gl256p 256m - bi t 3.0 - volt parallel flash memory with page mode
w29gl256p publication release date : jul 0 2 , 201 4 i revision a table of contents 1 general description ................................ ................................ ................................ ......... 1 2 features ................................ ................................ ................................ ................................ . 1 3 pin configuration ................................ ................................ ................................ ............... 2 4 block diagram ................................ ................................ ................................ ...................... 3 5 pin description ................................ ................................ ................................ ..................... 3 6 array architecture ................................ ................................ ................................ ........... 4 6.1 sect or address table ................................ ................................ ................................ ..... 4 7 functional descripti on ................................ ................................ ................................ .... 5 7.1 device bus operation ................................ ................................ ................................ ..... 5 7.2 instruction definitions ................................ ................................ ................................ ...... 6 7.2.1 reading array data ................................ ................................ ................................ .......... 6 7.2.2 page mode read ................................ ................................ ................................ .............. 7 7.2.3 de vice reset operation ................................ ................................ ................................ .... 8 7.2.4 standby mode ................................ ................................ ................................ ................... 8 7.2.5 output disable mode ................................ ................................ ................................ ........ 8 7.2. 6 write operation ................................ ................................ ................................ ................. 8 7.2.7 byte/word selection ................................ ................................ ................................ ......... 9 7.2.8 automatic programming of the memory array ................................ ................................ .. 9 7.2.9 erasing the memory array ................................ ................................ .............................. 10 7.2.10 erase suspend/resume ................................ ................................ ............................... 11 7.2.11 sector erase resume ................................ ................................ ................................ ... 11 7.2.12 program suspend/resume ................................ ................................ ........................... 12 7.2.13 program resume ................................ ................................ ................................ .......... 12 7.2.14 write buffer programming operation ................................ ................................ ............ 12 7.2.15 buffer write abort ................................ ................................ ................................ ......... 13 7.2.16 accelerated programming operation ................................ ................................ ............ 13 7.2.17 automatic select bus operation ................................ ................................ ................... 13 7.2.18 automatic select operations ................................ ................................ ......................... 14 7.2.19 automatic select instruction sequence ................................ ................................ ........ 14 7.2.20 enhanced variable io (evio) control ................................ ................................ .......... 15 7.2.21 hardware data protection options ................................ ................................ ............... 15 7.2.22 inherent data protection ................................ ................................ ............................... 15 7.2.23 power supply decoupling ................................ ................................ ............................. 15 7.3 enhanced sector protect/un - protect ................................ ................................ ............ 16 7.3.1 lock register ................................ ................................ ................................ .................. 17 7.3.2 individual (non - volatile) protection mode ................................ ................................ ....... 18 7.4 security sector flash memory region ................................ ................................ ......... 21 7.4.1 factory locked: security sector programmed and protected at factory ......................... 21 7.4.2 customer lockable: security sector not programmed or protected .............................. 21 7.5 instruct ion definition tables ................................ ................................ ......................... 22 7.6 common flash memory interface (cfi) mode ................................ ............................. 26 7.6.1 query instruction and common flash memory interface (cfi) mode ............................. 26
w29gl256p publication release date : jul 0 2 , 201 4 ii revision a 8 electrical character istics ................................ ................................ ......................... 30 8.1 absolute maximum stress ratings ................................ ................................ ............... 30 8.2 operating temperature and voltage ................................ ................................ ............ 30 8.3 dc characteristics ................................ ................................ ................................ ........ 31 8.4 switching test circuits ................................ ................................ ................................ .. 32 8.4.1 switching test waveform ................................ ................................ ............................... 32 8.5 ac characteristics ................................ ................................ ................................ ........ 33 8.5.1 instruction write operation ................................ ................................ ............................. 34 8.5.2 read / reset operation ................................ ................................ ................................ .. 35 8.5.3 erase/program operation ................................ ................................ ............................... 37 8.5.4 write operation status ................................ ................................ ................................ .... 46 8.5.5 word/byte configuration (#byte) ................................ ................................ ..... 50 8.5.6 deep power down mode ................................ ................................ ........................ 52 8.5.7 write buffer program ................................ ................................ .......................... 52 8. 6 recommended operating conditions ................................ ................................ ........... 53 8.6.1 at device power - up ................................ ................................ ................................ ........ 53 8.7 erase and programming performance ................................ ................................ ......... 54 8.8 data retention ................................ ................................ ................................ .............. 54 8.9 latch - up characteristics ................................ ................................ ............................... 54 8.10 pin capacitance ................................ ................................ ................................ ............ 54 9 package dimensions ................................ ................................ ................................ ......... 55 9.1 tsop 56 - pin 14x20mm ................................ ................................ ................................ 55 9.2 low - profile fine - pitch ball grid array, 64 - ball 11x13mm (lfba64) ............................ 56 10 ordering information ................................ ................................ ................................ ..... 57 10.1 ordering part number definitions ................................ ................................ ................. 57 10.2 valid part numbers and top side marking ................................ ................................ .. 58 11 history ................................ ................................ ................................ ................................ .. 59
w29gl256p publication release date : jul 0 2 , 201 4 iii revision a list of figures figure 3 - 1 lfbga64 top view ................................ ................................ ................................ ...... 2 figure 3 - 2 56 - pin standard tsop (top view) ................................ ................................ ........ 2 figure 4 - 1 block diagram ................................ ................................ ................................ ................. 3 figure 7 - 1 enhanced sector protect/un - protect ipb program algorithm ................................ ...... 16 figure 7 - 2 lock register program algorithm ................................ ................................ ................. 17 figure 7 - 3 ipb program algorithm ................................ ................................ ................................ . 19 figure 8 - 1 maximum negative overshoot ................................ ................................ ..................... 30 figure 8 - 2 maximum positive overshoot ................................ ................................ ....................... 30 figure 8 - 3 switch test circuit ................................ ................................ ................................ ........ 32 figure 8 - 4 switching test waveform ................................ ................................ ............................. 32 figure 8 - 5 instruction write operation waveform ................................ ................................ .......... 34 figure 8 - 6 read timing waveform ................................ ................................ ................................ 35 figure 8 - 7 #reset timing waveform ................................ ................................ ........................... 36 figure 8 - 8 automatic chip erase timing waveform ................................ ................................ ...... 37 figure 8 - 9 automatic chip erase algorithm flowchart ................................ ................................ .. 38 figure 8 - 10 automatic sector erase timing waveform ................................ ................................ ... 39 figure 8 - 11 automatic sector erase algorithm flowchart ................................ ............................... 40 figure 8 - 12 e rase suspend/resume flowchart ................................ ................................ .............. 41 figure 8 - 13 automatic program timing waveform ................................ ................................ .......... 42 figure 8 - 14 accelerated program timing waveform ................................ ................................ ....... 42 figure 8 - 15 ce# controlled write timing waveform ................................ ................................ ....... 43 figure 8 - 16 automatic programming algorithm flowchart ................................ .............................. 44 figure 8 - 17 silicon id read timing waveform ................................ ................................ ................ 45 figure 8 - 18 data# polling timing waveform (during automatic algorithms) ................................ .. 46 figure 8 - 19 status polling for word programming/erase ................................ ................................ 47 figure 8 - 20 status polling for write buffer program flowchart ................................ ....................... 48 figure 8 - 21 toggling bit timing waveform (during automatic algorithms) ................................ .... 49 figure 8 - 22 toggle bit algorithm ................................ ................................ ................................ ...... 50 figure 8 - 23 #byte timing waveform for read operations ................................ ........................... 51 figure 8 - 24 page read timing waveform ................................ ................................ ....................... 51 figure 8 - 25 deep power down mode waveform ................................ ................................ ............ 52 figure 8 - 26 write buffer program flowchart ................................ ................................ ................... 52 figure 8 - 27 ac timing at device power - up reference to #reset ................................ ............... 53 figure 9 - 1 tsop 56 - pin 14x20mm ................................ ................................ ................................ 55 figure 10 - 1 ordering part numbering ................................ ................................ .............................. 57
w29gl256p publication release date : jul 0 2 , 201 4 iv revision a list of tables table 5 - 1 pin description ................................ ................................ ................................ ................ 3 table 6 - 1 sector address ................................ ................................ ................................ ............... 4 table 7 - 1 device bus operation ................................ ................................ ................................ ..... 5 table 7 - 2 device bus operation (continue) ................................ ................................ .................... 5 table 7 - 3 polling during embedded program operation ................................ ............................... 9 table 7 - 4 polling during embedded sector erase operation ................................ ...................... 10 table 7 - 5 polling during embedded chip erase operation ................................ ......................... 11 table 7 - 6 polling during embedded erase suspend ................................ ................................ ... 11 table 7 - 7 polling during embedded program suspend ................................ ............................... 12 table 7 - 8 polling buffer write abort flag ................................ ................................ ..................... 13 table 7 - 9 auto select for mfr/device id/secure silicon/sector protect read ........................... 14 table 7 - 10 lock register bits ................................ ................................ ................................ ......... 17 table 7 - 11 sector protection status table ................................ ................................ ..................... 20 table 7 - 12 factory locked: security sector ................................ ................................ ................... 21 table 7 - 13 id reads, sector verify, and security sector entry/exit ................................ .............. 22 table 7 - 14 program, write buffer, cfi, erase and suspend ................................ ......................... 23 table 7 - 15 deep power down ................................ ................................ ................................ ........ 23 table 7 - 16 lock register and global non - volatile ................................ ................................ ......... 24 table 7 - 17 ipb functions ................................ ................................ ................................ ............... 24 table 7 - 18 volatile dpb functions ................................ ................................ ................................ . 25 table 7 - 19 cfi mode: id data values ................................ ................................ ............................ 26 table 7 - 20 cfi mode: system interface data values ................................ ................................ .... 27 table 7 - 21 cfi mode: device geometry data values ................................ ................................ .... 28 table 7 - 22 cfi mode: primary vendor - specific extended query data values ............................. 29 table 8 - 1 absolute maximum stress ratings ................................ ................................ ............... 30 table 8 - 2 operating temperature and voltage ................................ ................................ ............ 30 table 8 - 3 dc characteristics ................................ ................................ ................................ ........ 31 table 8 - 4 test specification ................................ ................................ ................................ .......... 32 table 8 - 5 ac characteristics ................................ ................................ ................................ ........ 34 table 8 - 6 ac characteristics #reset and ry/#by ................................ ................................ .... 35 table 8 - 7 ac characteristics word/byte configuration (#byte) ................................ ................. 50 table 8 - 8 ac characteristics for deep power down ................................ ................................ .... 52 table 8 - 9 ac characteristics at device power u p ................................ ................................ ....... 53 table 8 - 10 ac characteristics for erase and programming performance ................................ ..... 54 table 8 - 11 data retention ................................ ................................ ................................ .............. 54 ta ble 8 - 12 latch - up characteristics ................................ ................................ ............................... 54 table 8 - 13 pin capacitance ................................ ................................ ................................ ............ 54 table 10 - 1 valid part numbers and markings ................................ ................................ ................ 58 table 11 - 1 revision history ................................ ................................ ................................ ............ 59
w29gl256p publication release date : jul 0 2 , 201 4 1 revision a general description the w29gl256p parallel flash memory provides a storage solution for embedded system applications that require better performance, lower power consumption and higher density. the device has a random access speed of 90ns and a fast page access speed of 25ns, as well as significant ly faster program and erase time than the products available on the market today. the w29gl256p also offers special features such as compatible manufacturer id that makes the device industry standard compatible without the need to change firmware. 1 feature s ? 64k - word/128k - byte uniform sector architecture C total 256 uniform sectors ? 32 - word/64 - byte write buffer C reduces total program time for multiple - word updates ? 8 - word/16 - byte page read buffer ? secured silicon sector area C programmed and locked by the customer or during production C 128 - word/256 - byte sector for permanent, safe identification using an 8 - word/16 - byte random electronic serial number ? enhanced s ector p rotect using dynamic and individual mechanisms ? polling/toggling methods are used to detect the status of program and erase operation ? suspend and resume commands used for program and erase operations ? more than 100,000 erase/program cycles ? more than 20 - year data retention ? software and hardware write protection C write - pr otect all or a portion of memory C enable/disable protection with #wp pin C top or bottom array protection ? low power consumption ? deep power down mode ? industrial t emperature range ? faster erase and program time C erase is 1.5x faster than industry standard C program is 2x faster than industry standard C allows for improved production throughput and faster field updates ? cfi (common flash interface) support ? single 3v read/program/erase (2.7 - 3.6v ) ? enhanced variable i o control C all input levels (address, control, and dq) and output levels are determined by voltage on the e vio input. e vio ranges from 1.65 to v cc ? #wp/acc input C accelerates programming time (when v hh is applied) for greater throughput during system production C protects first or last sector regardless of sector protection settings ? hardware reset input (#reset ) resets device ? ready/#busy output (ry/#by) detects completion of program or erase cycle ? packages C 56 - pin tsop C 64 - ball lfbga
w29gl256p publication release date : jul 0 2 , 201 4 2 revision a 2 pin configuration figure 2 - 1 lfbga64 top view figure 2 - 2 56 - pin standard tsop (top view)
w29gl256p publication release date : jul 0 2 , 201 4 3 revision a 3 block diagram figure 3 - 1 block diagram 4 pin description symbol pin name a0 - a23 address inputs dq0 - dq14 data inputs/outputs dq15/a - 1 word mode dq15 is data input/output byte mode a - 1 is address input #ce chip enable #oe output enable #we write enable #wp/acc hardware write protect/ acceleration pin #byte byte enable #reset hardware reset ry/#by ready/busy status v cc power supply e vio enhanced variable io supply vss ground nc no connection table 4 - 1 pin description
w29gl256p publication release date : jul 0 2 , 201 4 4 revision a 5 array architecture 5.1 sect or address table sector sector address a23 - a16 sector size (kbyte/kword ) x8 start / finish x16 start / finish sa00 0000000 128/64 000000h 01ffffh 000000h 00ffffh sa01 0000001 128/64 020000h 03ffffh 010000h 01ffffh . . . . . . . . . . . . . . . . . . . . . sa 254 1 1111110 128/64 1 fc0000h 1 fdffffh f e0000h f effffh sa 255 1 1111111 128/64 1 fe0000h 1 ffffffh f f0000h f fffffh table 5 - 1 sector address note: the address range [ a23 :a - 1] in byte mode (#byte = vil ) or [ a23 :a0] in word mode (#byte = vih )
w29gl256p publication release date : jul 0 2 , 201 4 5 revision a 6 functional descripti on 6.1 d evice b us o peration mode select #reset #ce #we #oe address (4) data i/o dq[7:0] #byte #wp/acc v il v ih data i/o dq[15:8] device reset l x x x x high - z high - z high - z l/h standby mode v cc 0.3v v cc 0.3v x x x high - z high - z high - z h output disable h l h h x high - z high - z high - z l/h read mode h l h l ain dout dq [14:8]=high - z dq15=a - 1 dout l/h write h l l h ain din din note (1,2) accelerated program h l l h ain din din v hh table 6 - 1 device bus operation notes: 1. the first or last sector was protected if # wp/acc= vil . 2. when # wp/acc = vih , the protection conditions of the outmost sector depends on previous protection condi tions. refer to the enhanced protect feature. 3. dq[15:0] are input (din) or output (dout) pins according to the requests of instruction sequence, sector pro tection, or data polling algorithm. 4. in word mode (byte#= vih ), the addresses are a23 to a0. in byte mode (byte#= vil ), the addresses are a23 to a - 1 (dq 15), . description control inputs a23 ~12 a11 ~10 a9 a8 ~7 a6 a5 ~4 a3 ~2 a1 a0 dq [7:0] dq[15:8] #ce #we #oe byte word read silicon id manufacturer code l h l x x vhh x l x l l l ef x 00 device id cycle 1 l h l x x vhh x l x l l h 7e x 22 cycle 2 l h l x x vhh x l x h h l 22 x 22 cycle 3 l h l x x vhh x l x h h h 01 x 22 sector lock status verification (1) l h l sa x vhh x l x l h l 01/00 x x secure sector (h) (2) l h l x x vhh x l x l h h 99/19 x x secure sector (l) (2) l h l x x vhh x l x l h h 89/09 x x table 6 - 2 device bus operation (continue) notes: 1. sector unprotected code:00h. sector protected code:01h. 2. factory locked code: #wp protects high address sector: 99h. #wp pr otects low address sector: 89h . factory unlocked code: #wp protects high address sector: 19h. #wp protects low address sector: 09h
w29gl256p publication release date : jul 0 2 , 201 4 6 revision a 6.2 i nstruction d efinitions the device operation can be initiated by writing specific address and data commands or sequences into the instruction register. the device will be reset to reading array data when writing incorrect address and data values or writing them in the improper se quence. the addresses will be latched on the falling edge of #we or #ce, whichever happens later; while the data will be latched on the rising edge of #we or #ce, whichever happens first. please refer to timing waveforms. 6.2.1 reading array data the default sta te after power up or a reset operation is the read mode . to execute a read operation, the chip is enabled by setting #ce and #oe active and #we high . at the same time, the required address or status register location is provided on the address lines. the system reads the addressed location contents on the data io pins a fter the t ce and t oe timing requirements have been met. o utput data will not be accessible on the data io pins if either the device or its output s are not enabled by #ce or #oe being high, and the outputs will remai n in a tri - state condition . when the device completes an embedded memory operation (i.e., program, automatic chip erase or sector erase) successfully, it will return to the read mode and from any address in the memory array the data can be read. however, if the embedded operation fails to complete, by verifying the status register bit dq5 (exceeds time limit flag) going high during the operations, at this time system should execute a reset operation causing the device to return t o read mode. some operating states require a reset operation to return to read mode such as: ? time - out condition during a program or erase failed condition, indicated by the status register bit dq5 going high during the operation. failure during either of t hese states will prevent the device from automatically returning to read mode. ? during device auto select mode or cfi mode, a reset operation is required to terminate their operation. in the above two situations, the device will not return to the read mode unless a reset operation is executed (either hardware reset or software reset instruction) or the system will not be able to read array data. the device will enter erase - suspended read mode if the device receives an erase suspend instruction while in the s ector erase state. the erase operation will pause (after a time delay not exceeding 20s) prior to entering erase - suspend read mode. at this time data can be programmed or read from any sector that is not being erased. another way to verify device status is to read the addresses inside the sectors being erased. this will only provide the contents of the status register. program operation during erase - suspend read mode of valid sector(s) will automatically return to the erase - suspend read mode upon success ful completion of the program operation. an erase resume instruction must be executed to exit the erase - suspended read mode, at which time suspended erase operations will resume. erase operation will resume where it left off and continue until successful completion unless another erase suspend instruction is received.
w29gl256p publication release date : jul 0 2 , 201 4 7 revision a 6.2.2 page mode read the p age m ode r ead has page sizes of 16 bytes or 8 words. the higher addresses a[ 23: 3] accesses the desired page . to access a particular word or byte in a page , it is selec ted by a[2:0] for word mode and a[2:0,a - 1] for byte mode. page mode can be turned on by keeping page - read address constant and changing the intra - read page address es . the page access time is t aa or t ce , followed by t pa for the page read time. when #ce toggles, access time is t aa or t ce .
w29gl256p publication release date : jul 0 2 , 201 4 8 revision a 6.2.3 device reset operation pulling the #reset pin low for a period equal to or greater than t rp will return the device to read mode. if the device is performing a program or erase operation, the reset operation will take at most a period of t ready 1 before the device returns to read mode. the ry/#by pin will remain low (busy status) until the device retur ns to read mode. note, the device draws larger current if the #reset pin is held at voltages greater that gnd + 0.3v and less than or equal to v il . when the #reset pin is held a gnd 0.3v, the device only consumes reset (i cc 5 ) current. it is recommended to ti e the system reset signal to the #reset pin of the flash memory. this allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. executing the reset instruction will reset the devi ce back to the read mode in the following situations: ? during an erase instruction sequence, before the full instruction set is completed. ? sector erase time - out period ? erase failed, while dq5 is high. ? during program instruction sequence, before the full instruction set is completed, including the erase - suspended program instruction. ? program failed, while dq5 is high as well as the erase - suspended program failure. ? auto - select mode ? cfi mode ? the user must issue a reset instruction to reset the device back to the read mode when the device is in auto - select mode or cfi mode, or when there is a program or erase failure (dq5 is high). ? when the device is performing a programming (not program fail) or erasing (not erase fail) function, the device will ignore reset commands. 6.2.4 standby mode standby mode is entered when both #reset and #ce are driven to v cc 300mv (inactive state). at this time output pins are place d in the high impedance state regardless of the state of the #we or #oe pin s and the device will draw mini mal standby current (i cc 4 ). if the device is deselected during erase or program operation, the device will draw active current until the operation is completed. 6.2.5 output disable mode the #oe pin controls the state of the data io pins. if #oe is driven high (v ih ), all data io pins will remain at high impedance and if driven low, the data io pins will drive data ( #oe has no affect on the ry/by# output pin). 6.2.6 writ e operation to execute a write operation, chip enable (#ce) pin is driven low and the output enabl e (#oe) is pulled high to disable the data io pins to a high impedance state. the desired address and data should be present on the appropriate pins. addresses are latch ed on the falling edge of either #we or #ce and data is latched on the rising edge or e ither #ce or #we. to see an example, please refer to timing diagram s in figure 8 - 5 and figure 8 - 15 . if an invalid write instruction , not defined in this datasheet is written to the device, it may put the device in an undefined state.
w29gl256p publication release date : jul 0 2 , 201 4 9 revision a 6.2.7 byte/word selection to choose between the byte or word mode, the #byte input pin is used to select how the data is input/output on the data io pins and the organization of the array data. if the #byte pin is driven hi gh, word mode will be selected and all 16 data io pins will be active. if the #byte is pulled low, byte mode will be active and only data io dq[7:0] will be active. the remaining data io pins (dq[14:8]) will be in a high impedance state and dq15 becomes th e a - 1 address input pin. 6.2.8 automatic programming of the memory array t o program the memory array in byte or word mode , refer to the instruction definition tables for correct cycle defined instructions that include t he 2 u nlocking instruction cycles, the a0h program cycle instruction and subsequen t cycle s containing the specified address location and the byte or word desired data content, followed by the start of the embedded algorithm to automatically program the array. once the program instruction sequence has been executed, the internal state machine commences execut ion of the algorithms and timing necessary for programming and cell verification . i nclude d in this operation is generating suitable program pulses , checking cell threshold voltage (v t ) margins, and if any cells do not pass verification or have acceptable margins , repetitive program pulse sequence will be cycled again . the internal process mechanisms will protect cells that do pass margin and verification tests from being over - programmed by pro hibiting further program pulses to passing cells as failing cells continue to be run through the internal program ming sequence until the pass . this feature allows the user to only perform the auto - programming sequence once and the device state machine takes care of the program and verification process. array bits during programming can only change a bit status of 1 (erase state) to a 0 (programmed state) . it is not possible to do the reverse with a programming operation. this can only be done by first performing an erase operation. keep in mind , the internal write verification only checks and detects errors in cases where a 1 is not successfully programmed to 0. during the embedded programming algorithm process a ny commands written to the device will be ignored , except hardware reset or a program suspend instruction . hardware reset will terminate the program operation after a period of time , not to exceed 10s. if in the case a prog ram suspend was executed, the device will enter the program suspend read mode. when the embedded program algorithm is completed or the program is terminated by a hardware reset, the device will return to read mode. the user can check for completion by rea ding the following bits in the status register, once the embedded program operation has started : status dq7 dq6 dq5 dq1 ry/#by 1 in progress dq7# toggling 0 0 0 exceeded time limit dq7# toggling 1 n/a 0 table 6 - 3 polling during embedded program operation note: 1. ry/#by is an open drain output pin and should be connected to vcc through a high value pull - up resistor.
w29gl256p publication release date : jul 0 2 , 201 4 10 revision a 6.2.9 erasing the memory array sector erase and chip erase are the two possible types of erase operations executed on the memory array. sector erase operation erases one or more selected sectors and this can be simultaneous. chip erase operation erases the entire memory array, except fo r any protected sectors. 6.2.9.1 sector erase the sector erase operation returns all selected sectors in memory to the 1 state, effectively clear ing all data . this action requires six instruction cycles to commence the erase operation. the unlock sequence is t h e first two cycles, followed by the configuration cycle, the fourth and fifth are also unlock cycles, and the sector erase instruction is the sixth cycle . an internal 50s time - out counter is started o nce the sector erase instruction sequence has been co mpleted . during this time, additional sector addresses and sector erase commands may be issued , thus allowing for multiple sector s to be selected and erased simultaneously. once the 50s time - out counter has reached its limit , no addition al command instruc tion s will be accepted and the embedded sector erase algorithm wil l commence . note, that the 50s time - out counter restart s after every sector erase instruction sequence. the device will abort and return to read mode, i f any instruction other than sector erase or erase suspend is attempted during the time - out per iod . once the embedded sector erase algorithm begins, all instructions except erase suspend or hardware reset will be ignored . the hardware reset will abort the erase operation a nd return the device to the read mode. the embedded sector erase algorithm status can be verified by the following: status dq7 dq6 dq5 dq3 1 dq2 ry/#by 2 time - out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 exceeded time limit 0 toggling 1 1 toggling 0 table 6 - 4 polling during embedded sector erase operation note : 1. the dq3 status bit is the 50s time - out indicator. when dq3=0, the 50s time - out counter has not yet reached zero and the new sector erase instruction maybe issued to specify the address of another sector to be erased. when dq3=1, the 50s time - out counter has expired and the sector erase operation has already begun. erase suspend is the only valid instruction that maybe issued once the embedded erase operation is underway. 2. ry/#by is an open drain output pin and should be connected to vcc through a high val ue pull - up resistor. 3. when an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data changes in the protected sector(s). dq7 will output 0 and dq6 will toggle briefly (100s or less) before aborting and returning the device to read mode. if unprotected sectors are also specified, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. dq2 is a localized indicator showing a specified sector is undergoing erase operation or not. dq2 toggles when user reads at the addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode).
w29gl256p publication release date : jul 0 2 , 201 4 11 revision a 6.2.9.2 chip erase the chip e rase operation returns all memory locations containing a bit state of 0 to the 1 state, effectively clearing all data. this action requires six instruction cycles to commence the erase operation. the unlock sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are also unlock cycles, and the sixth cycle initiates the chip erase operation. once the chip erase algorithm begins, no other instruction will be accepted. however, if a hardware reset is executed or the operating voltage is below acceptable levels, the chip erase operation will be terminated and automatically returns to read mode. the embedded chip erase algorithm status can be verified by the following: status dq7 dq6 dq5 dq2 ry/#by 1 in progress 0 toggling 0 toggling 0 exceeded time limit 0 toggling 1 toggling 0 table 6 - 5 polling during embedded chip erase operation note: 1. ry/#by is an open drain pin and should be connected to vcc through a high value pull - up resistor. 6.2.10 erase suspend/resume if there is a sector erase operation in progress, an erase suspend instruction is the only valid instruction that may be issued. once the erase suspend instruction is executed during the 50s time - out period following a sector erase instruction, the time - o ut period will terminate right away and the device will enter erase - suspend read mode. if an erase suspend instruction is executed after the sector erase operation has started, the device will not enter erase - suspended read mode until approximately 20s (5 s typical) time has elapsed. to determine the device has entered the erase - suspend read mode, use dq6, dq7 and ry/#by status to verify the state of the device. once the device has entered erase - suspended read mode, it is possible to read or program any se ctor(s) except those being erased by the erase operation. only the contents of the status register is present when attempting to read a sector that has been scheduled to erase or be programmed when in the suspend mode. a resume instruction must be executed and recommend check ing dq6 toggle bit status, before issuing another erase instruction . the status register bits can be verified to determine the current status of the device: status dq7 dq6 dq5 dq3 dq2 dq1 ry/#by erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle n/a 1 erase suspend read in non - erase suspended sector data data data data data data 1 erase suspend program in non - erase suspended sector dq7# toggle 0 n/a n/a n/a 0 table 6 - 6 polling during embedded erase suspend instruction sets such as read silicon id, sector protect verify, program, cfi query and erase resume can also be executed during erase - suspend mode, except sector and chip erase. 6.2.11 sector erase resume only in the erase - suspended read mode can t he sector erase resume instruction be a valid command. once e rase resumes , another erase suspend instruction can be executed , but allow a 400s interval between erase resume and the next erase suspend instruction .
w29gl256p publication release date : jul 0 2 , 201 4 12 revision a 6.2.12 program suspend/resume once a program operation is in progress , a program suspend is the only valid instruction that maybe executed . verifying if the device has entered the program - suspend read mode after executing the program - suspend instruction, can be done by checking the ry/#by and dq6. programming should halt within 15s maximum (5s typical). any sector(s) can be read except those being program suspended. trying to read a sector being progr am suspended is invalid. before another program operation can be executed, a resume instruction must be performed and dq6 toggling bit status has to be verified. use the status register bits shown in the following table to determine the current state of th e device: status dq7 dq6 dq5 dq3 dq2 dq1 ry/# b y program suspend read in program suspended sector invalid 1 program suspend read in non - program suspended sector data data data data data data 1 table 6 - 7 polling during embedded program suspend instruction sets such as read silicon id, sector protect verify, program, cfi query can also be executed during program/ erase - suspend mode . 6.2.13 program resume the program resume instruction is valid only when the device is in program - suspended mode. once the program resumes, a nother program suspend instruction can be executed. insure there is at least a 5s interval between program resume and the next suspend instruction . 6.2.14 write buffer programming operation write buffer pr ogramming operation, p rograms 64bytes or 32words in a two step programming operation. to begin execution of the write buffer programming, start with the first two unlock cycles, the third cycle writes the programming sector address destination followed by the write buffer load i nstruction (25h). t he fourth cycle repeats the sector address, while the write data is the n umber of intended w ord l ocations to be written minus one. (example, if the number of word locations to be written is 9 , then the value would be 8 h.) the 5 th cycle is the first starting address/data set. this will be the first pair to be programmed and consequentially , set s the write - buffer - page address. repeat cycle 5 format for each additional address/data sets to be w ritten to the buffer. keep in mind all sets must remain within the write buffer page address range. if not, operation will abort. the write - buffer - page is selected by choosing address a[2 3 :5]. the second step will be t o program the contents of the writ e buffer page . this is done with one cycle, containing the sector address that was used in step one and the write to buffer program confirm instruction (29h). standard suspend/resume commands can be used during the operation of the write - buffer . also, on ce the write buffer programming operation is finished, itll return to the normal read mode. write buffer programming can be conducted in any sequence. however the cfi functions, autoselect, secured silicon sector are not functional when program operation is in progress. multiple write buffer programming operations on the same write buffer address range without intervention erase is accessible . any bit in a write buffer address range cannot be programmed from 0 back to 1.
w29gl256p publication release date : jul 0 2 , 201 4 13 revision a 6.2.15 buffer write abort write buffer pr ogramming sequence will abort, if the following condition takes place : ? the word count minus one loaded is bigger than the page buffer size (32) during, number of locations to program. ? sector address written is not the same as the one specified during th e write - buffer - load instruction. ? if the address/data set is not inside the write buffer page range which was set during cycle 5s first initial write - buffer - page select address/data set. ? no program confirm instruction after the assigned number of data load cycles. after write buffer abort, the status register will be dq1=1, dq7 = data# (last address loaded ), dq6=toggle, dq5=0. this status represents a write buffer programming operation was aborted. a write - to - buffer - abort reset instruction sequence has to be written to reset the device back to the read array mode . dq1 is the bit for buffer write abort. when dq1=1, the device will abort from buffer write operation and go back to read status register shown in the following table: status dq7 dq6 dq5 dq3 dq 2 dq1 ry/# b y buffer write busy dq7# toggle 0 n/a n/a 0 0 buffer write abort dq7# toggle 0 n/a n/a 1 0 buffer write exceeded time limit dq7# toggle 1 n/a n/a 0 0 table 6 - 8 polling buffer write abort flag 6.2.16 accelerated programming operation t he device will enter the accelerated programming mode b y applying high voltage ( v hh ) to the #wp/acc pin. accelerated programming mode allows the system to skip the normal unlock sequences instruction and program byte/word locations directly. the current drawn from the #wp/acc pin d uring accelerated programming is no more that i acc1 . important note : do not exceed 10 accelerated programs per sector. (#wp/acc should not be held at vhh for any other function except for program ming or damage to the device may occur.) 6.2.17 automatic select bus operation there are basically t w o methods to access automatic selection operations ; automatic select instructions through software commands and high voltage applied to a9. see automatic select instruction sequence later on in this section for details of equivalent instruction operations that do not require the use of v hh . the following five bus operations require a9 to be raised to v hh . 6.2.17.1 sector lock status verification to verify the protected state of any sector using bus operations , e xecute a read operation with v hh applied to a9, the sector address present on address pins a[ 23 :12], address pins a6, a3, a2, and a0 held low , and address pins a1 held high . if dq0 is low , the secto r is considered not protected, and if dq0 is high , the sector is considered to be protected. 6.2.17.2 read silicon manufacturer id code winbonds 29gl - p/29gl - s families of parallel flash memories feature an industry standard compatible manufacturer id code of efh . to verify the silicon manufacturer id code, execute a read operation with vhh applied to the a9 pin and address pins a6, a3, a2, a1 and a0 are held low. the id code can then be read on data bits dq[7:0] .
w29gl256p publication release date : jul 0 2 , 201 4 14 revision a 6.2.17.3 read silicon device id code to verify the silicon d evice id code s , execute a read operation with v hh applied to the a9 pin a nd address p ins a6, a3, a2, a1, and a0 have several bit combination s to return t he winbond device id code s of 7e h , 22 h or 01h, which is shown on the data bits dq[7:0]. see table 7 - 2 . 6.2.17.4 read indicator bit dq7 for security sector high and low address to verify that the se curity sector has been factory locked, execute a read operation with v hh applied to a9 , address pins a6, a3, and a2 are held low, and address pins a1 and a0 are held high. if the securi ty sector has been factory locked , the code 99h(highest address sector) or 89h(lowest address sector) will be shown on the data bits dq[7:0]. otherwise, the factory unlocked code of 19h(h)/09(l) will be sh own . 6.2.18 automatic select operations the automatic select instruction show in table 7 - 1 3 can be executed if the device is in one of the following modes; read, program suspended, erase - suspended read, or cf i. at which time t he user can issue (two unlock cycles followed by the automatic select instruction 90h) to enter automatic select mode. once in the automatic select mode, the user can query the manufacturer id, device id, security sector locked status, or sector protected status multiple times without executing the unlock cycles and a automatic select instruction (90h) again. once in automatic select mode, executing a reset instruction (f0h) will return the device back to the valid mode from which it left when the automatic selec t mode was first executed. another way previously mention ed to enter automatic select mode is to use one of the bus operation shown table 7 - 2 in device bus operation . once the high voltage ( v hh ) is removed from the a9 pin, the d evice will return back to the valid mode from which it left when the automatic select mode was first executed . 6.2.19 automatic select instruction sequence accessing the manufacturer id, device id, and verifying whether or not secured silicon is locked and whether or not a sector protected is the purpose of automatic select mode . the re are four instruction cycles that comprise the automatic select mode . the f irst two cycles are write unlock commands , followed by the automatic select i nstruction (90h) . the fourth cycle is a read cycle, and the user may read at any address any number of times without entering another instruction sequence. to exit the automatic s elect mode and back to read array, t he reset instruction is necessary. no other instructions are allowed except the reset instruction once automatic select mode has been selected. refer to the following table for more detail ed information. address data (h ex) representation manufacturer id word x00 ef byte x00 ef device id w29gl256p word x01/0e/0f 227e/2222 /2201 byte x02/1c/1e 7e/2 2 /01 secure silicon word x03 99/19(h) factory locked/unlocked 89//09(l) byte x06 99/19(h) factory locked/unlocked 89/09(l) sector protect verify word (sector address) x02 00/01 unprotected/protected byte sector address) x04 00/01 unprotected/protected table 6 - 9 auto select for mfr/device id/secure silicon/sector protect read
w29gl256p publication release date : jul 0 2 , 201 4 15 revision a 6.2.20 enhanced variable io ( e vio ) control the enhanced variable io (e vio ) control allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and dq signals). e vio range is 1.65 to v cc . for example, a e vio of 1.65 - 3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. 6.2.21 hardware data protection options hardware data protection is the second of the two main sector protections offered by the w29gl 256 . 6.2.21.1 #wp/acc option by se tting the #wp/acc pin to v il , the highest or lowest sector (device specific) is protect ed from all erase/program operations. if #wp/acc is set high , the highest and lowest sector revert back to the previous protected/unprote cted state . note: the max input load current can increase, if #wp/acc pin is at v ih when the device is put into standby mode. 6.2.21.2 vcc write protect th is device will not accept any write instruction s when v cc is less that v wpt ( vcc write protect threshold ) . this prevents data from inadvertently being altered during power - up, power - down, a temporary power loss or to the low level of v cc . if v cc is lower that v wpt , th e device a utomatically resets itself and will ignore write cycles until v cc is greater than v wpt . once v cc rises above v wpt , insure that the proper signals are on the control pins to avoid unexpected program or erase operations. 6.2.21.3 write pulse glitch protection pulses less than 5ns are viewed as glitches for control signals #ce, #we, and #oe and will not be considered for valid write cycle s . 6.2.21.4 power - up write inhibit t he device ignores the first instruction on the rising edge of #we , if upon powering up the device, #we and #ce are set at v il and #oe is set at v ih . 6.2.21.5 logical inhibit a w rite cycle is ignored when either #ce is at v ih , #we is at v ih , or #oe is at v il . a valid write cycle requires both #ce and #we are at v il with #oe at v ih . 6.2.22 inherent data protection the device built - in mechanism will reset to read mode during power up t o avoid accidental erasure or programming. 6.2.22.1 instr uction completion in valid instruction sets will result in the memory returning to read mode . only upon a successful completion of a valid instruction set will the device begin its erase or program operation.. 6.2.22.2 power - up sequence t he device is placed in read mode , during power - up sequence . 6.2.23 power supply decoupling t o reduce noise effects , a 0.1f capacitor is recommended to be connected between v cc and gnd.
w29gl256p publication release date : jul 0 2 , 201 4 16 revision a 6.3 enhanced sector protect/un - protect this device is set from the factory in the individual protection mode of the enhanced sector protect scheme . t he user can disable or enable the programming or erasing operation to any individual sector or whole chip. the figure below helps describe an overview of these methods. the device defaults to the individual mode and all sectors are unprotected when shipped from the factory. the following flow chart shows the detailed algorithm of enhanced sector protect: figure 6 - 1 enhanced sector protect/un - protect ipb program algorithm start individual protection mode (default) set ipb lock bit ipb lock bit locked all ipb not changeable dynamic write protect bit (dpb) sector array individual protect bit (ipb) dpb=0 sector protect dpb=1 sector unprotect ipb lock bit unlocked ipb is changeable dpb 0 dpb 1 dpb 2 dpb + n . . . . sa 0 sa 1 sa 2 sa + n . . . . ipb 0 ipb 1 ipb 2 ipb + n . . . . ipb=0 sector protect ipb=1 sector unprotect ipb=0 ipb=1
w29gl256p publication release date : jul 0 2 , 201 4 17 revision a 6.3.1 lock register user can choose secured silicon sector protection bit for security sector protection method via setting the lock register bit , dq 0 . lock register is a 16 - bit one time programmable register. once progr ammed dq 0 , will be loc ked in that mode permanently. once the instruction set entry instruction sequence for the lock register bits is issued, all sectors re ad and write functions are disabled until lock register exit sequence has been executed. the memory sectors and extended memory sector protection is configured using the lock register . dq[15: 1 ] dq0 dont care table 6 - 10 lock register bits figure 6 - 2 lock register program algorithm start write data aah, address 555h write data 55 h, address 2aa h write data 40 h, address 555h write data a 0 h, addre ss dont care write program data , address dont care data # polling algorithm fail reset instruction done dq5=1 no no yes pass exit lock register instruction yes lock register instruction set entry lock register data prog ram
w29gl256p publication release date : jul 0 2 , 201 4 18 revision a 6.3.2 individual (non - volatile) protection mode 6.3.2.1 individual protection bits ( ipb ) the individual protection bit (ipb) is a nonvolatile bit, one bit per sector, with endurance equal to that of the flash memory array. before erasing , ipb preprogramming and verification is managed by the device, so no monitoring is necessary. the individual protection bits are set sector by sector by the ipb program instruction. once a ipb is set to 0, the linked sector is protected, blocking any program and/or erase functions on that sector. the ipb cannot be erased individually, but executing the all ipb erase instruction will erase all ipb simultaneously. read and write functions are disable d when ipb programming is going on for all sectors until this mode exits. in case one of the protected sectors need to be unprotected, first, the ipb lock bit must be set to 1 by performing one of the following: power - cycle the device or perform a hardw are reset. second, an all ipb erase instruction needs to be performed. third, individual protection bits need to be set once again to reflect the desired settings and finally, the ipb lock bit needs to be set once again which locks the individual protecti on bits and the device functions normally once again. executing an ipb read instruction to the device is required to verify the programming state of the ipb for any given sector. refer to the ipb program algorithm flow chart below for details. note : ? while ipb lock bit is set, program and/ or erase instructions will not be executed and times out without programming and/ or erasing the ipb . ? for best protection results , it is recommended to execute the ipb lock bit set instruction early on in the boot code . also , protect the boot code by holding wp#/acc = v il . note that the ipb and dpb bits perform the same when wp#/acc = v hh , and when wp#/ acc =v ih . ? while in the ipb command mode, r ead within that sector will bring the ipb status back for that sector. all read mus t be executed by the read mode. ? issuing the ipb instruction set exit will reset the device to normal read mode enabling reads and writes for the array . 6.3.2.2 dynamic protection bits (dpb ) dynamic protection allows the software application s to easily protect se ctors against unintentional change s, although , the protection can be readily disabled when changes are needed . all dynamic protection b it s (dpb) are individually linked to their associated sector s and these volatile bits can be modif ied individual ly (set or cleared) . the dpb provide protection scheme s for only unprotected sectors that have their associated ipb cleared. to change a dp b, the dpb instruction set entry must be executed first and then either the dpb set (programmed to 0 ) or dpb clear (erase d to 1 ) commands have to be executed. this places each sector in the protected or unprotected state separately. to exit the dpb mode, execute the dpb instruction set exit instruction. note : ? when the parts are first shipped, the ipb are cleared (erased to 1 ) and upon power up or reset, the dpb can be set or cleared.
w29gl256p publication release date : jul 0 2 , 201 4 19 revision a figure 6 - 3 ipb program algorithm note: 1. ipb program/erase status polling flowchart: check dq6 toggle, when dq6 stop toggle, the read status is 00h/01h ( 00 h for program and 01h for erase, otherwise the status is fail and exit. 6.3.2.3 individual protection bit lock bit the individual protection bit loc k bit ( ipblk ) is a global lock bit to control all ipb states . it is a singular volatile bit . if the ipblk is set (0) , all ipb are locked and all sectors are protected or unprotected according to their individual ipb . when ipblk =1 (cleared), all ipb are u nlock ed and allow ed to be set or cleared . to clear the ipb l ock b it , a hardware reset or a power - up cycle must be executed . . ipb instruction set entry program ipb read dq[7:0] twice read dq[7:0] twice read dq[7:0] twice dq5=1? dq6=toggle ? program fail write reset cmd dq6=toggle ? wait 500s pass ipb instruction set exit dq0= 1 (erase) or 0 (program) no no no no yes yes yes yes
w29gl256p publication release date : jul 0 2 , 201 4 20 revision a sector protection status sector status dpb ipb lk ipb clear clear clear unprotect, dpb and ipb are changeable clear clear set protect, dpb and ipb are changeable clear set clear unprotect, dpb is changeable clear set set protect, dpb is changeable set clear clear protect, dpb and ipb are changeable set clear set protect, dpb and ipb are changeable set set clear protect, dpb is changeable set set set protect, dpb is changeable table 6 - 11 sector protection status table
w29gl256p publication release date : jul 0 2 , 201 4 21 revision a 6.4 security sector flash memory region a n extra memory space length of 128 words is used as t he security sector r egion which can be factory locked or customer lockable . to enquire about the lock status of the device , the c ustomer can issue a security sector protect verify or security sector factory protect verify using automatic select address 03h and dq7. the security sector region is unprotected when shipped from factory and the security silicon indicator bit (dq7) is set to "0" for a customer lockable device. the security sector region is protected when shipped from factory and the security silicon sector ind icator bit is set to "1" for a factory - locked device. 6.4.1 factory locked: security sector programmed and protected at factory in a factory locked device, the security sector is permanently locked prior to factory ship ment the esn occupies addresses 00000h to 0000fh in byte mode or 00000h to 00007h in word mode since the device has a 16 - byte (8 - word) esn (electronic serial number) in the security region. security silicon sector address range standard factory locked express flash factory locked customer lockable 000000h - 000007h esn esn or determined by customer determined by customer 000008h - 00007fh in accessible determined by customer table 6 - 12 factory locked: security sector 6.4.2 customer lockable: security sector not programmed or protected important not ice; o nce the security silicon sector is protected (lock register otp dq0 = 0, security sector indicator dq7 bit=0) , there is no way to unprotect the security silicon sector and the content s of the memory region can no longer be programmed . once the security silicon is locked and verified, an exit security sector region instruction must be executed to get back to the read array mode. a power cycle, or a hardware reset will also return the device to read array mod e. t h is region can act as extra memory space when this security feature is not utilized. it is important to note, the security sector region is a one time programmable (otp) region. you can overwrite a word, but you cannot change the state of a programmed cell.
w29gl256p publication release date : jul 0 2 , 201 4 22 revision a 6.5 instruction definition tables instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6 th bus cycle add data add data add data add data add data add data read mode word add data byte add data reset mode word xxx f0 byte xxx f0 automatic select silicon id word 555 aa 2aa 55 555 90 x 00 ef byte aaa aa 555 55 aaa 90 x 00 ef device id word 555 aa 2aa 55 555 90 x01 id1 x0e id2 x0f id3 byte aaa aa 555 55 aaa 90 x0 2 id1 x 1 c id2 x 1 e id3 factory protect verify word 555 aa 2aa 55 555 90 x03 99/19(h) 89/09(l) byte aaa aa 555 55 aaa 90 x06 99/19(h) 89/09(l) sector protect verify word 555 aa 2aa 55 555 90 (sa)x02 00/01 byte aaa aa 555 55 aaa 90 (sa)x04 00/01 security sector region word 555 aa 2aa 55 555 88 byte aaa aa 555 55 aaa 88 exit security sector word 555 aa 2aa 55 555 90 xxx 00 byte aaa aa 555 55 aaa 90 xxx 00 table 6 - 13 id reads, sector verify, and security sector entry/exit
w29gl256p publication release date : jul 0 2 , 201 4 23 revision a instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6 th bus cycle add data add data add data add data add data add data program word 555 aa 2aa 55 555 a0 add data byte aaa aa 555 55 aaa a0 add data write to buffer program word 555 aa 2aa 55 sa 25 sa n - 1 wa wd wbl wd byte aaa aa 555 55 sa 25 sa n - 1 wa wd wbl wd write to buffer program abort reset word 555 aa 2aa 55 555 f0 byte aaa aa 555 55 aaa f0 write to buffer program confirm word sa 29 byte sa 29 chip erase word 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase word 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 cfi read word 55 98 byte aa 98 program/erase suspend word xxx b0 byte xxx b0 program/erase resume word xxx 30 byte xxx 30 table 6 - 14 program, write buffer, cfi, erase and suspend wa=write address, wd=write data, sa=sector address, n - 1=word count, wbl=writebuffer location, id1/id2/id3: refer to table 7 - 2 for detail id. instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle add data add data add data add data add data deep power down enter word 555 aa 2aa 55 xxx b9 byte aaa aa 555 55 xxx b9 exit word xxx ab byte xxx ab table 6 - 15 deep power down
w29gl256p publication release date : jul 0 2 , 201 4 24 revision a instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle add data add data add data add data add data lock register lock register instruction set entry word 555 aa 2aa 55 555 40 byte aaa aa 555 55 aaa 40 program word xxx a0 xxx data byte xxx a0 xxx data read word xxx data byte xxx data lock register instruction exit word xxx 90 xxx 00 byte xxx 90 xxx 00 global non - volatile ipb instruction set entry word 555 aa 2aa 55 555 c0 byte aaa aa 555 55 aaa c0 ipb program word xxx a0 sa 00 byte xxx a0 sa 00 all ipb erase word xxx 80 00 30 byte xxx 80 00 30 ipb status read word sa 00/01 byte sa 00/01 table 6 - 16 lock register and global non - volatile instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle add data add data add data add data add data global non - volatile ipb instruction set exit word xxx 90 xxx 00 byte xxx 90 xxx 00 global volatile freeze ipb instruction set entry word 555 aa 2aa 55 555 50 byte aaa aa 555 55 aaa 50 ipb lock set word xxx a0 xxx 00 byte xxx a0 xxx 00 ipb lock status read word xxx 00/01 byte xxx 00/01 ipb lock instruction set exit word xxx 90 xxx 00 byte xxx 90 xxx 00 table 6 - 17 ipb functions
w29gl256p publication release date : jul 0 2 , 201 4 25 revision a instruction 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle add data add data add data add data add data volatile dpb instruction set entry word 555 aa 2aa 55 555 e0 byte aaa aa 555 55 aaa e0 dpb set word xxx a0 sa 00 byte xxx a0 sa 00 dpb clear word xxx a0 sa 01 byte xxx a0 sa 01 dpb status read word sa 00/01 byte sa 00/0 1 dpb instruction set exit word xxx 90 xxx 00 byte xxx 90 xxx 00 table 6 - 18 volatile dpb functions notes : 1. it is not recommended to use any other code that is not in the instruction definition table which can potentially enter the hidden mode. 2. for the ipb lock and dpb status read "00" represents lock (protect), "01" represents unlock (unprotect).
w29gl256p publication release date : jul 0 2 , 201 4 26 revision a 6.6 common flash memory interface (cfi) mode 6.6.1 query instruction and common flash memory interface (cfi) mode through common flash interface ( cfi ) operations it is possible to access the operating characteristics, structure and vendor specif ic information , such as identifying information, memory size, byte/word configuratio n, operating voltages and timing information of this device. from the read array mode writing cfi read instruction 98h to the address "55h"/"aah" (word/byte , respectively ), the device will gain access to the cfi query mode. once in the cfi mode data can be read using the addresses given in table 7 - 19 thru 7 - 22 . a reset instruction must be executed to exit cfi mode and the device will return to read array mode. cfi mode: identification data values (all values in these tables are hexadecimal ) description address (word mode) address (byte mode) data query - unique asii string qry 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h primary vendor instruction set and control interface id code 13h 26h 0006 h 14h 28h 0000h address for primary algorithm extended query table 15h 2ah 0040h 16h 2ch 0000h alternate vendor instruction set and control interface id code 17h 2eh 0000h 18h 30h 0000h address for alternate algorithm extended query table 19h 32h 0000h 1ah 34h 0000h table 6 - 19 cfi mode: id data values
w29gl256p publication release date : jul 0 2 , 201 4 27 revision a cfi mode: system interface data values description address (word mode) address (byte mode) data v cc supply minimum program/erase voltage 1bh 36h 0027h v cc supply maximum program/erase voltage 1ch 38h 0036h vpp supply minimum program/erase voltage 1dh 3ah 0000h vpp supply maximum program/erase voltage 1eh 3ch 0000h typical timeout per single word/byte write, 2 n s 1fh 3eh 0003h typical timeout for maximum - size buffer write, 2 n s (00h, not support) 20h 40h 0004 h typical timeout per individual block erase, 2 n ms 21h 42h 0009h typical timeout for full chip erase, 2 n ms (00h, not support) 22h 44h 0011 h maximum timeout for word/byte write, 2 n times typical 23h 46h 0003h maximum timeout for buffer write, 2 n times typical 24h 48h 0005h maximum timeout per individual block erase, 2 n times typical 25h 4ah 0003h maximum timeout for chip erase, 2 n times typical (00h, not support) 26h 4ch 0002h table 6 - 20 cfi mode: system interface data values
w29gl256p publication release date : jul 0 2 , 201 4 28 revision a cfi mode: device geometry data values description address (word mode) address (byte mode) data device size = 2 n in number of bytes 27h 4eh 0019 h flash device interface description (02=asynchronous x8/x16) 28h 50h 0002h 29h 52h 0000h maximum number of bytes in buffer write = 2 n (00h, not support) 2ah 54h 0006h 2bh 56h 0000h number of erase regions within device (01h:uniform, 02h:boot) 2ch 58h 0001h index for erase bank area 1: [2e,2d] = # of same - size sectors in region 1 - 1 [30, 2f] = sector size in multiples of 256k - bytes 2dh 5ah 00 f fh 2eh 5ch 0000h 2fh 5eh 0000h 30h 60h 0002h index for erase bank area 2 31h 62h 0000h 32 h 64h 0000h 33h 66h 0000h 34h 68h 0000h index for erase bank area 3 35h 6ah 0000h 36h 6ch 0000h 37h 6eh 0000h 38h 70h 0000h index for erase bank area 4 39h 72h 0000h 3ah 74h 0000h 3bh 76h 0000h 3ch 78h 0000h table 6 - 21 cfi mode: device geometry data values
w29gl256p publication release date : jul 0 2 , 201 4 29 revision a cfi mode: primary vendor - specific extended query data values description address (word mode) address (byte mode) data query - primary extended table, unique ascii string, pri 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h major version number, ascii 43h 86h 0031h minor version number, ascii 44h 88h 0033h unlock recognizes address (0= recognize, 1= don't recognize) 45h 8ah 001c h erase suspend (2= to both read and program) 46h 8ch 0002h sector protect (n= # of sectors/group) 47h 8eh 0001h temporary sector unprotect (1=supported) 48h 90h 0000h sector protect/chip unprotect scheme 49h 92h 0008h simultaneous r/w operation (0=not supported) 4ah 94h 0000h burst mode (0=not supported) 4bh 96h 0000h page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) 4ch 98h 0002h minimum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4dh 9a h 0095h maximum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4eh 9c h 00a5h wp# protection 04=uniform sectors bottom wp# protect 05=uniform sectors top wp# protect 4fh 9eh 00xx h program suspend (0=not supported, 1=supported) 50h a0h 0001h table 6 - 22 cfi mode: primary vendor - specific extended query data values
w29gl256p publication release date : jul 0 2 , 201 4 30 revision a 7 electrical character istics 7.1 a bsolute m aximum s tress r atings surrounding temperature with bias - 65c to +125c storage temperature - 65c to +150c v cc voltage range - 0.5v to +4.0v e vio voltage range - 0.5v to +4.0v a9, #wp/acc voltage range - 0.5v to + 10.5 v other pins voltage range - 0.5v to v cc +0.5v output short circuit current (less than one second) 200 ma table 7 - 1 absolute maximum stress ratings 7.2 operating temperature and voltage industrial grade surrounding temperature (ta) - 40c to +85c full v cc range supply voltage +2.7v to 3.6v e vio range supply voltage (1) 1.65v to v cc table 7 - 2 operating temperature and voltage note : 1. the evio feature was designed to support voltages from 1.65v to vcc. devic e testing is conducted at evio= v cc . 2. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 3. specifications contained within the following tables are subject to change. 4. during voltage transitions, all pins may overshoot v ss to - 2.0v and v cc to +2.0v for periods up to 20ns, see below figure. 5. specification for the w29gl256p is preliminary. see preliminary designation at the end of this docum ent. figure 7 - 1 maximum negative overshoot figure 7 - 2 maximum positive overshoot vss vss - 2.0v 20ns 20ns 20ns vcc +2.0v vcc 20ns 20ns 20ns
w29gl256p publication release date : jul 0 2 , 201 4 31 revision a 7.3 dc c haracteristics description symbol conditions min typ . max unit input leak i li others 2.0 a wp#/acc 5 .0 a a9 leak i lit a9=10.5v 35 a output leak i lo 1.0 a read current i cc 1 #ce= v il , #oe= v ih , v cc = v cc max: f =1mhz 6 + 20 ma #ce= v il , #oe= v ih , v cc = v cc max : f=5mhz 20 30 ma #ce= v il , #oe= v ih , v cc = v cc max : f=10mhz 45 55 ma v cc page read current i cc 2 #ce= v il , #oe= v ih , v cc = v cc max : f=10mhz 7 15 ma #ce= v il , #oe= v ih , v cc = v cc max : f=33mhz 1 5 25 ma write current i cc 3 #ce=v il , #oe=v ih , v cc =v cc max 20 30 ma standby current i cc 4 #ce, #reset=vcc 0.3v, #oe=v ih , v cc = v cc max , vil=v ss + 0.3v/ - 0.1v 70 100 a reset current i cc 5 v cc = v cc max , #reset enabled, other pins disabled 70 100 a sleep mode current (1) i cc 6 v cc =v cc max, v ih =v cc 0.3, v il =v ss +(0.3v/ - 0.1v), #wp/acc=v ih 70 100 a v cc deep power down current i dpd 1 5 a accelerated pgm current, wp#/a cc , pin(word/byte) i acc 1 #ce= v il , #oe= v ih 10 20 ma accelerated pgm current, v cc pin, (word/byte) i acc 2 #ce= v il , #oe= v ih 20 30 ma input low voltage v il - 0.1 0.3x e vio v input high voltage v ih 0.7x e vio e vio +0.3 v very high voltage for auto select/ accelerated program v hh 9.5 10.5 output low voltage v ol i ol =100a 0.45 v ou t put high voltage v oh i oh = - 100a 0.85x e vio v vcc write protect threshold v wpt 2.3 2.5 v table 7 - 3 dc characteristics note: 1. sleep mode enable the lower power when address remain stable for taa +30n s.
w29gl256p publication release date : jul 0 2 , 201 4 32 revision a 7.4 switching t est c ircuits figure 7 - 3 switch test circuit test condition all speeds unit output load 1ttl gate output load capacitance 30 pf rise/fall times 5 ns input pulse levels 0.0 - e vio v input timing measurement reference level (if e vio w29gl256p publication release date : jul 0 2 , 201 4 33 revision a 7.5 ac c haracteristics description symbol v cc =2.7v~3.6v alt std min typ max units valid data output after address e vio = v cc ? 3 v t acc t aa 90 ns e vio =1.65v to v cc (1) 100 ns page access time e vio =v cc t pacc t pa 25 ns e vio =1.65v to v cc (1) 35 ns valid data output after #ce low e vio = v cc ? 3 v t ce 90 ns e vio =1.65v to v cc (1) 100 ns valid data output after #oe low e vio =v cc t oe 25 ns e vio =1.65v to v cc (1) 35 ns read period time e vio = v cc ? 3 v t rc 90 ns e vio =1.65v to v cc (1) 100 ns data output high impedance after #oe high t df 20 ns data output high impedance after #ce high t df 20 ns output hold time from the earliest rising edge of address, #ce, #oe t oh 0 ns write period time t wc 90 ns command write period time t cwc 90 ns address setup time t as 0 ns address setup time to #oe low during toggle bit polling t aso 15 ns address hold time t ah 45 ns address hold time from #ce or #oe high during toggle bit polling t aht 0 ns data setup time t ds 30 ns data hold time t dh 0 ns v cc setup time t vcs 35 s chip enable setup time t cs 0 ns chip enable hold time t ch 0 ns output enable setup time t oes 0 ns output enable hold time read t oeh 0 ns toggle & data# polling 10 ns #we setup time t ws 0 ns #we hold time t wh 0 ns #ce pulse width t cp t cepw 35 ns #ce pulse with high t cph t cepwh 30 ns #we pulse width t wp 35 ns #we pulse width high t wph 30 ns program/erase active time by ry/#by e vio = v cc ? 3v t busy 90 ns e vio =1.65v to v cc 100 ns read recover time before write (#oe high to #we low) t ghwl 0 ns read recover time before write (#oe high to # ce low) t ghel 0 ns 32 - word write buffer program operation t whwh 1 1 00 s effective write buffer program operation word t whwh 1 6 s
w29gl256p publication release date : jul 0 2 , 201 4 34 revision a description symbol v cc =2.7v~3.6v alt std min typ max units accelerated effective write buffer operation per word t whwh 1 4.8 s program operation byte t whwh 1 6 200 s program operation word t whwh 1 10 200 s acc 32 - word program operation t whwh 1 1 00 s sector erase operation t whwh 2 0.3 2 sec sector erase timeout t sea 50 s release from deep power down mode t rdp 100 200 s table 7 - 5 ac characteristics note: 1. the evio feature was designed to support voltages from 1.65v to vcc. devic e testing is conducted at evio= v cc . 7.5.1 instruction write operation figure 7 - 5 instruction write operation waveform data in t ds t dh valid address t ah t as t oes t wp t wph t cs t ch t cwc v ih v il v ih v il v ih v il v ih v il v ih v il #ce #we #oe addresses data
w29gl256p publication release date : jul 0 2 , 201 4 35 revision a 7.5.2 read / reset operation figure 7 - 6 read timing waveform 7.5.2.1 ac characteristics description symbol setup speed unit alt std #reset pulse width (during automatic algorithm) t rp t rp 1 min 10 s #reset pulse width (not during automatic algorithm) t rp t rp 2 min 500 ns #reset high time before read t rh min 200 ns ry/#by recovery time (to #ce, #oe goes low) t rb t rb 1 min 0 ns ry/#by recovery time (to #we goes low) t rb t rb 2 min 50 ns #reset low (during automatic algorithm) to read or write t ready t ready 1 max 20 s #reset low (not during automatic algorithm) to read or write t ready t ready 2 max 500 ns table 7 - 6 ac characteristics #reset and ry/#by #ce #we #oe addresses outputs v ih v il v ih v il v ih v il v ih v il v oh v ol high z high z add valid data valid t ce t oeh t oe t df t aa t oh t rc
w29gl256p publication release date : jul 0 2 , 201 4 36 revision a figure 7 - 7 #reset timing waveform #ce, #oe #we ry/#by #reset reset timing during automatic algorithms reset timing not during automatic algorithms #ce, #oe ry/#by #reset t rb 1 t rb 2 t ready 1 t rp 1 t rh t rp 2 t ready 2
w29gl256p publication release date : jul 0 2 , 201 4 37 revision a 7.5.3 erase/program operation figure 7 - 8 automatic chip erase timing waveform t whwh 2 t ch t wp t wph t cs t ghwl t wc t as t ah t ds t dh t busy t rb read status valid address v. add 555h 2aah 55h 10h in progress complete last 2 erase command cycles #ce #we #oe address data ry/#by
w29gl256p publication release date : jul 0 2 , 201 4 38 revision a figure 7 - 9 automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 10h address 555h data# polling algorithm or toggle bit algorithm auto chip erase completed data = ffh ? no yes
w29gl256p publication release date : jul 0 2 , 201 4 39 revision a figure 7 - 10 automatic sector erase timing waveform #ce #we #oe address data ry/#by read status t ch t wp t cs t wph t whwh 2 t ghwl t sea t wc t as t ds t dh t ah t busy t rb valid address v. add. in progress completed 2aah 55h 30h 30h 30h last 2 erase command cycle sector add 0 sector add 1 sector add n
w29gl256p publication release date : jul 0 2 , 201 4 40 revision a figure 7 - 11 automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 30h sector address last sector to erase data# polling algorithm or toggle bit algorithm data= ffh auto sector erase completed no no yes yes
w29gl256p publication release date : jul 0 2 , 201 4 41 revision a figure 7 - 12 erase suspend/resume flowchart start write data b0h toggle bit checking dq6 not toggled read array or program reading or programming end write data 30h continue erase another erase suspend? erase suspend erase resume no no no yes yes yes
w29gl256p publication release date : jul 0 2 , 201 4 42 revision a figure 7 - 13 automatic program timing waveform figure 7 - 14 accelerated program timing waveform #ce #we #oe address data ry/#by 555h program address valid address v. add a0h pdata status dout last 2 program command cycles t ch t wp t wph t ghwl t cs t whwh 1 t as t ah t ds t dh t busy t rb last 2 read status cycles #wp/acc v hh v il or v ih (9.5v ~ 10.5v) 250ns 250ns v il or v ih
w29gl256p publication release date : jul 0 2 , 201 4 43 revision a figure 7 - 15 ce# controlled write timing waveform #we #ce #oe address data ry/#by 555h pgm add valid address v.add a0h pd status dout t cepw t whwh 1 or t whwh 2 t cepwh t ghel t as t ah t ds t dh t busy
w29gl256p publication release date : jul 0 2 , 201 4 44 revision a figure 7 - 16 automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write data a0h address 555h write program data/address data# polling algorithm or toggle bit algorithm read again data: program data? last word to be programmed auto program completed next address no no yes yes
w29gl256p publication release date : jul 0 2 , 201 4 45 revision a figure 7 - 17 silicon id read timing waveform vcc a9 a0 a1 a2 add #ce #we #oe dq [15:0] 3v v hh v ih v il v ih v ih v ih v ih v ih v oh v ih v il v il v il v il v il v il v ol v il v ih t aa t aa t aa t aa t ce t oe t oh t oh t oh t oh t df manufacturer id device id cycle 1 device id cycle 2 device id cycle 3 data out data out data out data out
w29gl256p publication release date : jul 0 2 , 201 4 46 revision a 7.5.4 write operation status figure 7 - 18 data# polling timing waveform (during automatic algorithms) #ce #we #oe address dq7 dq[6 - 0] ry/#by t ce t ch t oe t oeh t rc t df t aa t oh t busy valid address valid address valid data high z true complement status data valid data high z true complement status data
w29gl256p publication release date : jul 0 2 , 201 4 47 revision a figure 7 - 19 status polling for word programming/erase notes : 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. d q7 should be rechecked even d q5="1" because d q7 may change si multaneously with d q5 . start read dq[7:0] at valid address (1) dq7=data#? dq5=1? read dq[7:0] at valid address dq7=data#? (2) fail pass no yes yes no yes
w29gl256p publication release date : jul 0 2 , 201 4 48 revision a figure 7 - 20 status polling for write buffer program flowchart notes: 1. for programming, valid address means program address. 2. for erasing, valid address means erase sectors address. 3. dq7 should be rechecked even dq5="1" because dq7 may change simultaneously with dq5. start read dq[7:0] at last write address (1) dq7=data#? dq1=1? only for write buffer program dq5=1? read dq[7:0] at last write address (1) dq7=data#? (2) fail pass write buffer abort no yes yes no no yes no yes
w29gl256p publication release date : jul 0 2 , 201 4 49 revision a figure 7 - 21 toggling bit timing waveform (during automatic algorithms) t ch t ce t oe t oeh t aa valid address valid address t df t aht t aso t oh t busy (first read) (second read) (stop toggling) valid address valid address #ce #we #oe address dq6&2 ry/#by valid status valid status valid status valid status
w29gl256p publication release date : jul 0 2 , 201 4 50 revision a figure 7 - 22 toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as dq5 changes to "1". 7.5.5 word/byte configuration ( # byte) description symbol test setup all speed options unit #ce to #byte from l/h t elfl /t elfh max. 5 ns #byte from l to output hiz t flqz max. 30 ns #byte from h to output active t fhqv min. 90 ns table 7 - 7 ac characteristics word/byte configuration (#byte) start read dq[7:0] twice (1) dq6 toggle? dq5=1? read dq[7:0] twice dq6 toggle? program/erase fail write reset cmd program/erase completed no yes no yes no yes
w29gl256p publication release date : jul 0 2 , 201 4 51 revision a figure 7 - 23 #byte timing waveform for read operations figure 7 - 24 page read timing waveform dout dq[7:0] dout dq[14:0] valid address dout dq15 t fhqv dq[14:0] dq15/a - 1 #byte t elfh #oe #ce
w29gl256p publication release date : jul 0 2 , 201 4 52 revision a 7.5.6 deep power down mode description symbol typ. max #we high to release from deep power down mode t rdp 100s 200s #we high to deep power down mode t dp 10s 20s table 7 - 8 ac characteristics for deep power down figure 7 - 25 deep power down mode waveform 7.5.7 write buffer program figure 7 - 26 write buffer program flowchart t dp t rdp xxxh (dont care) xxxh 555h 2aah aah 55h b9h abh standby mode deep power down mode standby mode #ce #we address data write cmd: data= aah , add=555h write cmd: data=55h, add=2aah write cmd: data=25h, add=sa write cmd: data=pwc, add=sa write cmd: data=pgm data, add=pgm add want to abort? pwc=0? write cmd: data=29h, add=sa polling status write reset cmd to return to read mode write abort reset cmd to return to read mode write a different sector address to cause abort return to read mode pass? fail? write buffer abort? pwc=pwc - 1 no yes no yes yes no yes yes no sa = sector address of the page to be programmed pwc = program word count no
w29gl256p publication release date : jul 0 2 , 201 4 53 revision a 7.6 r ecommended o perating c onditions 7.6.1 a t device power - up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power - up. if the timing in the figure is ignored, the device may not operate correctly. figure 7 - 27 ac timing at device po wer - up reference to #reset description symbol min max unit alt std reset low time from rising edge of vcc t vcs 35 s reset low time from rising edge of e vio t vios t evios 35 s reset high time before read t rh 200 ns table 7 - 9 ac characteristics at device power up t vcs t evios t rh v cc e vio #ce #reset min min
w29gl256p publication release date : jul 0 2 , 201 4 54 revision a 7.7 erase and programming performance parameter limits units min typ (1) max (2) chip erase time 80 50 0 sec sector erase time 0. 3 2 sec chip programming time 48 224 sec word programming time 10 200 s total write buffer time 1 00 s acc total write buffer time 1 00 s erase/program cycles 100,000 cycles table 7 - 10 ac characteristics for erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0v v cc . programming specifica tions assume checkerboard data pattern. 2. maximum values are measured at v cc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. erase/program cycles comply with jedec jesd - 47e & a117a standard. 4. exclude 00h program before erase operation. 7.8 data retention parameter condition m in max unit data retention 55c 20 years table 7 - 11 data retention 7.9 l atch - up c haracteristics parameter min max input voltage different with gnd on #wp/acc and a9 pins - 1.0v 10.5v input voltage difference with gnd on all normal input pins - 1.0v 1.5 x v cc v cc current - 100ma +100ma all pins included except v cc . test condition is v cc =3.0v, one pin per test. table 7 - 12 latch - up characteristics 7.10 pin c apacitance description parameter test set typ. max unit control pin capacitance cin2 vin=0 7.5 9 pf output capacitance cout vout=0 8.5 12 pf input capacitance cin vin=0 6 7.5 pf table 7 - 13 pin capacitance
w29gl256p publication release date : jul 0 2 , 201 4 55 revision a 8 package dimensions 8.1 tsop 56 - pin 14x20mm symbol dimension in mm dimension inch min nom max min nom max a - - 1.2 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.17 0.22 0.27 0.007 0.009 0.011 b1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.10 - 0.21 0.004 - 0.008 c1 0.10 0.13 0.16 0.004 0.005 0.006 d 20.00 bsc 0.787 bsc d1 18.40 bsc 0.724 bsc e 14.00 bsc 0.551 bsc l 0.50 0.60 0.70 0.020 0.024 0.028 l1 0.25 bsc 0.010 bsc e 0.5 bsc 0.020 bsc r 0.08 - 0.35 0.003 - 0.008 0 - 8 0 - 8 figure 8 - 1 tsop 56 - pin 14x20mm pin 1 identifier a a1 a2 r l1 l 0.80 ref bottom ejector pin cavity # mark 1 28 29 56 d d1 e b 0.10 c with plating c c1 b b1 base metal e
w29gl256p publication release date : jul 0 2 , 201 4 56 revision a 8.2 low - profile fine - pitch ball grid array, 64 - ball 11x13mm (l fba 64) symbol dimension (mm) note min nom max a - - 1.40 profile a1 0.40 - ball height a2 0.60 - body thickness d 13.00 bsc body size e 11.00 bsc body size d1 7.00 bsc matrix footprint e1 7.00 bsc matrix footprint n 64 ball count ?b 0.5 0.6 0.7 ball diameter ee 1.00 bsc ball pitch ed 1.00 bsc ball pitch sd/se 0.50 bsc solder ball placement none depopulated solder balls figure 8 - 2 lfbga 64 - ball 11x13mm d e a b 0.07 (2x) top view pin a1 corner 0.07 c (2x) ee sd pin a1 corner ? b bottom view se e1 ed d1 h g f e d c b a 8 7 6 5 4 3 2 1 0.15 c 0.15 c 0.25 c // a a2 a1 c side view 64x ? b ? 0.20 ? 0.10 m m m m c c b a
w29gl256p publication release date : jul 0 2 , 201 4 57 revision a 9 ordering information 9.1 ordering part number definitions figure 9 - 1 ordering part numbering notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. contact winbond sales for secured sector lock options. w 29gl 256 p h 9 t winbond standard product w: winbond product family 29gl: 3v (vcc=2.7~3.6v) density 256 : 256m b product version p: 58 nm sector type h: evio=1.65v to vcc (2.7~3.6v), uniform sector, highest address sector protected l: evio=1.65v to vcc (2.7~3.6v), uniform sector, lowest address sector protected access time 9: industrial 90ns packages t: tsop - 56, green (rohs compliant) b: lf bga64, green (rohs compliant)
w29gl256p publication release date : jul 0 2 , 201 4 58 revision a 9.2 valid part numbers and top side marking the following table provides the valid part numbers for the w29gl256p parallel flash memory . please contact winbond for specific availability by density and package type. winbond parallel memories use a 12 - di git product number for ordering . package type density product number top side marking tsop - 56 256m b w29gl256p h 9 t w29gl256p h 9 t tsop - 56 256m b w29gl256p l9 t w29gl256p l9 t lfbga64 256m b w29gl256p h 9 b w29gl256p h9b lfbga64 256m b w29gl256p l9b w29gl256p l9b table 9 - 1 valid part numbers and markings
w29gl256p publication release date : jul 0 2 , 201 4 59 revision a 10 history version date page description a 0 7 - 0 2 - 201 4 - first release table 10 - 1 revision history trademarks winbond is a trademark of winbond electronics corporation . all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore , winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wher ein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from su ch improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described h erein at any time, without notice.

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